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Signal Integrity Architect Santa Clara, California, Systems E

Job in Santa Clara, Santa Clara County, California, 95053, USA
Listing for: Qualcomm
Full Time position
Listed on 2026-07-22
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 220200 - 330400 USD Yearly USD 220200.00 330400.00 YEAR
Job Description & How to Apply Below
Position: Signal Integrity Architect Santa Clara, California, United States of America + 1 more Systems E[...]
## Signal Integrity Architect Santa Clara, California, United States of America Apply Now Find out how well you match with this jobJob ID3084142##
** Company:
** Qualcomm Technologies, Inc.##
** Job Area:
** Engineering Group, Engineering Group  Systems Engineering
** General

Summary:

** Qualcomm Data Center team is developing High performance, Energy efficient server solution for data center applications. We are looking for highly talented, innovative, teamwork-oriented individuals for our cutting-edge technology work!
** Our Mission
** We are dedicated to transforming the industry by reimagining silicon and developing next-generation computing platforms. By joining our team, you’ll collaborate with world-class engineers to create innovative solutions that push the limits of performance, energy efficiency, and scalability. Our focus is on developing reference platforms based on Qualcomm's Snapdragon SoC, delivering a comprehensive solution that includes hardware, software, reference designs, user guides, SDKs, and more.

** Position:
Signal Integrity Architect
** We are seeking an experienced
** Signal Integrity Architect** (individual contributor) to develop high-performance signal integrity (SI) solutions tailored for advanced server applications. In this role, you will work closely with the platform team and collaborate with cross-functional teams, including software, firmware, packaging, product management, and component suppliers. You will contribute to the definition, analysis, and verification of SI for high-speed interconnects — with a primary focus on
** CXL
* * and
** GPIO/LSIO
** interfaces — across PCB and system levels for data center servers.
** Key Responsibilities
*** Own SI analysis, simulation, and design closure for CXL 2.0/3.0 interfaces, including channel budget development, , margin analysis and lab methodology support.
* Collaborate with SoC, applications engineering, packaging, and system design teams to define and implement system interconnects that meet the unique demands of high-end server environments.
* Contribute to SI guidelines development, provide feedback on PCB stack-ups, routing constraints, via structure design, and material selection.
* Develop   full-topology SI models, simulations, and final designs across assigned interface domains.
* Perform SI analysis on 2.5D/3D structures and contribute to the establishment of design guidelines for advanced packaging integration.
* Own SI analysis and design guidelines for GPIO/LSIO interfaces such as SPI, I3C, and proprietary paralle interface including signal integrity characterization, termination, and compliance.
* Support customer-facing SI collateral development — guidelines, application notes, and simulation models for CXL interfaces.
* Develop design automation tools and methodologies. Set technical direction for SI aspects of design within your area of ownership and drive innovating design methodologies
* Prepare and present technical documentation and reports to stakeholders, including engineering teams, senior management, customers, and suppliers.
** Qualifications
* ** Master’s degree in Electrical or Computer Engineering, with a specialization in Signal Integrity (SI).
* 8+ years of experience in SI analysis, simulation, and measurement of high-speed digital systems.
* Strong knowledge of SI fundamentals, including power distribution networks (PDN), EMIR, transmission line theory, crosstalk, S-parameters, and channel simulations.
* Expertise in CXL 2.0/3.0 specifications and/or PCIe Gen5+ Ser Des standards, including channel simulation and compliance methodology.
* Experience with GPIO, LSIO, and low-speed interface SI characterization and design guidelines.
* Familiarity with Ser Des standards (PCIe, CXL, USB, Ethernet, etc.).
* Experience owning end-to-end methodologies, encompassing packaging, PCBs, connectors and cabling
* Proficiency with 2D/2.5D/3D EM simulation tools such as ANSYS HFSS/HFSS3DL, Cadence Sigrity, Dassault Systèmes CST, Keysight ADS, and Synopsys' HSPICE.
* Hands-on experience creating complex SI models and performing both frequency and time-domain simulations.
* Proficiency in Unix/Linux environments and…
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