SoC Logic Design Engineer

SoC Logic Design Engineer

As a SoC Logic Design Engineer, you will play a pivotal role in advancing Intel's next-generation System on Chip (SoC) designs. In this role, you will focus on developing high-quality logic designs, coding at the register transfer level (RTL), and optimizing performance to deliver energy-efficient and secure solutions. Your contributions will directly impact Intel's ability to deliver innovative and market-leading semiconductor technologies.

This position resides within Intel's leading-edge silicon engineering group, which is dedicated to designing, developing, and scaling advanced semiconductor solutions for a wide range of applications. This team focuses on integrating cutting-edge technology, ensuring quality standards, and driving innovation that supports Intel's commitment to delivering world-class products and solutions.

• Develop logic designs and RTL code for SoC blocks and subsystems aligned with architectural and microarchitectural specifications
• Integrate IP blocks and subsystems into comprehensive full-chip SoC designs
• Participate in the definition of architecture and microarchitecture features of the blocks being designed
• Optimize logic designs to meet power, performance, area, and timing goals using advanced tools and strategies
• Conduct quality checks to ensure design integrity and readiness for physical implementation
• Review verification plans to confirm accuracy in tested design features and implement corrective measures for failing RTL tests
• Apply secure development practices to address security models and objectives in hardware design
• Collaborate with IP providers to integrate and validate IPs at the SoC level
• Ensure quality assurance compliance for smooth IP/SoC handoff and design readiness

• Collaborative Communicator — Proven ability to work across teams and convey complex technical ideas clearly and effectively
• Innovative Thinker — Enthusiasm for staying ahead of industry trends and applying creative approaches to SoC design challenges
• Execution-Driven — Demonstrated success in delivering complex projects from concept through implementation

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related specialized field with 4+ years of hands-on experience in logic design, RTL development, and microarchitecture implementation, or Master's degree with 3+ years of experience in the same fields
• The years of experience must include:
• RTL coding languages such as Verilog
• Expertise in SoC integration, SoC clocking, and low-power design methodologies
• Experience in strategies for timing, power convergence, and physical implementation optimization
• Hands-on experience with Clock Domain Crossing techniques and Network-on-Chip (NoC) architectures
• Working experience with AMBA protocols such as CHI, AXI, AHB, and APB

Preferred Qualifications

• Hands-on experience from spec to timing closure in at least one SoC/ASIC design

We encourage you to bring your expertise and passion for innovation to Intel, where your contributions will shape the future of semiconductor technology and empower industries worldwide.

Experienced Hire

Shift 1 (United States of America)

US, Texas, Austin

US, California, Santa Clara, US, Oregon, Hillsboro

All qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $- USDThe range displayed on this job posting reflects the minimum and…