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Senior STA & Constraints Engineer – Timing Closure SoC
Job in
Santa Clara, Santa Clara County, California, 95053, USA
Listed on 2026-07-24
Listing for:
AMD
Full Time
position Listed on 2026-07-24
Job specializations:
-
Engineering
Hardware Engineer, Test Engineer, Electronics Engineer
Job Description & How to Apply Below
AMD is seeking a STA/Constraints Engineer in Santa Clara, CA to own end‑to‑end timing constraints and closure for SOCs and sub‑systems. You will work with Fellows, Principal Engineers and architects, guiding RTL designers and PD teams across cross‑functional global groups.
The role requires expertise in STA, timing signoff, and PD tooling (SNPS PT/GCA, ICC2/FC), Verilog RTL, and scripting. You’ll contribute to robust clock design, SDC development, and power-aware implementations.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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