STA​/Constraints Engineer

What You Do at AMD

At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture.

We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

The STA/Constraints Engineer is responsible for developing Full Chip constraints and timing closure. The person will work closely with Fellows, Principal Engineers, Architects, and collaborate with cross‑functional worldwide teams across Physical Design, Timing Analysis, Synthesis, Physical Verification, Power signoff, and mentor/coach/guide Design Engineers.

• Own end‑to‑end delivery of designs (SOC and sub‑system integration) from the perspective of timing constraints and timing signoff.
• Work closely with the SOC Architecture team for SOC clocks and STA for statistical timing target goals.
• Understand clock design requirements and ensure they are correctly set up in SDC.
• Understand timing margins (LVF/SSTA/variations, etc.) on the latest tech nodes and work with timing methodology teams for current and future projects.
• Understand design requirements, timelines and various milestones of a project and deliver FCT closure accordingly.
• Collaborate with CAD and EDA vendors to strengthen AMD timing closure and constraints methodology.
• Responsible for CDC/LINT, timing closure, lower‑power implementation and netlist quality check with RTL designers and PD teams.
• Work on SDC development, STA (Static Timing Analysis), shift‑left of timing closure, and Clock Domain Crossing.

• Industry experience in STA, constraints, timing signoff and physical design.
• Expert user of industry‑standard PD tools like SNPS PT/GCA (must) and ICC2/FC (desired).
• Strong understanding of DFT timing concepts, MBIST, top‑level clock implementation, place‑and‑route flows—including floor planning, placement, CTS and route.
• Experience with Perl/TCL/Shell/Python scripting and Verilog RTL design.
• Excellent presentation and inter‑communication skills.
• Experience with Verilog RTL design/implementation and participation in large digital ASIC projects.
• Experience with physical design is a plus.
• Experience with lower‑power design methodology.
• Strong English speaking, writing and documentation skills.
• Self‑motivated, good at task scheduling, and proficient in time management.

• Bachelor or Master’s degree in Microelectronics/Integrated Circuit Science or related field (preferred).

Santa Clara, CA

This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal‑opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.