Principal RTL Lead – Speed Ethernet; ASIC

Principal RTL Lead – High Speed Ethernet (ASIC)

Mos Chip is a semiconductor and embedded system design company with a focus on Embedded, Turnkey ASICs, Mixed Signal IP, Semiconductor & Product Engineering and IoT solutions catering to Aerospace & Defense, Consumer Electronics, Automotive, Medical and Networking & Telecommunications.

We are seeking a seasoned Principal RTL Lead to spearhead the development of next-generation Ethernet subsystems. This isn't just about moving packets; it's about defining the architecture for 400G, 800G, and beyond. As the technical lead, you will own the logic that powers the world's fastest data centers, ensuring ultra-low latency and rock-solid reliability at massive scale.

Candidate will lead a high-caliber team of designers to implement high-speed Ethernet IP (MAC/PCS/PMA) into our custom ASIC silicon. Your role is a blend of deep technical execution and strategic mentorship—steering the team through the complexities of multi-lane alignment, Forward Error Correction (FEC), and high-speed clocking challenges.

• Technical Leadership: Act as the primary architect for the Ethernet subsystem. You'll define micro-architecture for high-bandwidth data paths and complex control logic.
• Protocol Mastery: Own the implementation of IEEE 802.3 standards, including RS-FEC (254, 256), multi-lane distribution (MLD), and auto-negotiation/link training (AN/LT).
• High-Speed Logic Design: Solve the "hard problems" of networking: managing massive bus widths (eg, 1024-bit+), minimizing logic depth for timing closure, and handling complex CDC across asynchronous boundaries.
• Front-End Integration: Lead the integration of third-party Ser Des IP and ensure seamless interoperability between the electrical physical layer and the digital MAC.
• Design for Excellence: Drive best practices in coding (System Verilog), power optimization (UPF), and lint/CDC/RDC analysis to ensure first-pass silicon success.

• 10+ years of experience in RTL design with at least 3-4 successful tape-outs in advanced process nodes (7nm, 5nm, or 3nm).
• Deep, hands-on experience with 100G/400G/800G Ethernet protocols and the underlying sub-layers (MAC, PCS, FEC).
• Expert knowledge of the full front-end ASIC flow—from architectural spec to synthesis, formal verification, and post-silicon bring-up.
• Proven ability to close timing on high-frequency designs and manage complex clocking architectures.
• Proficiency in Python or Perl for creating sophisticated design-generation and analysis tools.
• Experience with IEEE 1588 (PTP) hardware stamping for precision timing.
• Familiarity with CXL or PCIe Gen 5/6 protocols.
• Direct experience working with physical design teams on timing and congestion mitigation.

Experience:

10+ Years

Location:

Bay Area, California

Contract Duration: 6 Plus months

Shift: General

Work Week:
Monday to Friday