IP Design Verification Engineer

IP Design Verification Engineer

The Role and Impact As an IP Design Verification Engineer, you will play a pivotal role in Intel's mission to deliver world-class silicon solutions. In this role, you will ensure the functionality and reliability of cutting-edge IP logic designs, collaborating with a diverse set of teams to bring innovative products to life. Your work will not only validate high-performance designs but also directly contribute to Intel's success in shaping the future of technology.

If you're passionate about solving complex challenges and driving innovation, this is your opportunity to make a meaningful impact.

Key Responsibilities
- Develop and execute comprehensive IP verification plans to ensure alignment with microarchitecture specifications.

- Design and maintain test benches and verification environments to support high-coverage validation.

- Define, implement, and run system simulation models to analyze design functionality, power, and timing.

- Replicate, root cause, and debug issues in the presilicon environment, driving resolution through corrective measures.

- Collaborate closely with architects, RTL developers, and physical design teams to enhance verification processes for complex architectural and microarchitectural features.

- Document test plans and lead technical reviews with design and architecture teams to ensure robust verification coverage.

- Maintain and improve existing functional verification infrastructure, ensuring it meets evolving requirements.

- Participate in defining verification infrastructure and methodologies essential for functional design validation.

Qualifications

Minimum Qualifications
- Bachelor's or BS degree and/or prolonged course of study in a specialized field, or equivalent experience as required.

- 6 or more years of experience with a Bachelor's degree, 4 or more years with a Master's degree, or 2 or more years with a PhD.

- Proficiency in System Verilog and RTL design.

- Hands-on experience in creating verification test environments and implementing test plans.

- Strong debugging skills and experience with IP microarchitecture validation and debug.

- Solid understanding of problem-solving methodologies for complex technical challenges.

Preferred Qualifications
- Experience in group problem-solving and collaboration within cross-functional teams.

- Familiarity with advanced verification methodologies and tools.

- Demonstrated ability to analyze and improve existing verification infrastructure.

- Effective communication skills, with the ability to document and present outcomes and technical insights.

Job Type: Experienced Hire

Shift: Shift 1 (United States of America)

Primary

Location:

US, California, Santa Clara

Additional Locations:

Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $- USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
* Job posting details (such as work model, location or time type) are subject to change.