Senior Design Verification Engineer

We are looking for talented Design Verification Engineers to help verify and deliver Velaura’s next-generation Physical AI SoC. In this role, you will work closely with architects, RTL engineers, software engineers, and system teams to verify complex hardware blocks and system-level behavior across the entire platform. You will helpestablish confidence in the correctness, performance, reliability, and safety of the architecture—from individual RTL blocks to complete HW/SW systems runningreal-world workloads.

We welcome engineers at all experience levels who enjoyunderstanding systems, finding corner cases, and solving challenging technical problems.

Velaura Careers

• Develop and execute verification strategies for key portions of the Velaura SoC.
• Build verification environments using System Verilog, UVM, C/C++, assertions, formal verification, emulation, and related methodologies.
• Collaborate with architects and RTL engineers to define verification plans, coverage goals, and correctness criteria.
• Verify compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other critical SoC infrastructure.
• Perform HW/SW co-verification involving firmware, drivers, runtime software, and operating system interactions.
• Verify performance, latency, bandwidth, QoS, and real-time system behavior under representative workloads.
• Develop assertions, checkers, scoreboards, and automated verification infrastructure.
• Participate in emulation, FPGA prototyping, and pre-silicon software bring-up activities.
• Drive bug investigation, root-cause analysis, and debug across hardware and software boundaries.
• Post-silicon debug and root cause analysis.
• Leverage modern engineering tools, including AI-assisted verification workflows, to improve productivity, quality, and coverage.
• Contribute to a culture of technical excellence and continuous improvement.

• 10+ Years of experience verifying complex digital systems.
• Strong analytical and problem-solving skills.
• Strong understanding of computer architecture, microarchitecture, SoCarchitecture and digital design fundamentals.
• Experience in understanding low power methodologies and verification criteria.
• Strong understanding of CDC issues, clocking and reset verification.
• Experience with System Verilog, UVM, C/C++, assertions, coverage-drivenverification, and related methodologies.
• Familiarity with formal verification techniques and tools.
• Experience with emulation, FPGA prototyping, or pre-silicon validationenvironments.
• Understanding of memory systems, interconnect fabrics, caches, DMA engines,processors, or accelerator architectures.
• Experience debugging complex system-level issues.
• Ability to work effectively in a collaborative, multidisciplinary engineering environment.