Senior SystemVerilog RTL Design Engineer – IP/PHY
Job in
Santa Clara, Santa Clara County, California, 95053, USA
Listed on 2026-07-27
Listing for:
Intel
Full Time
position Listed on 2026-07-27
Job specializations:
-
Engineering
Systems Engineer, Hardware Engineer, Electronics Engineer
Job Description & How to Apply Below
Intel's HIPD team seeks a senior Logic design engineer for UCIE PHY IP in datacenter/server designs. You will develop RTL, define architecture features, and ensure design quality from RTL to timing convergence.
The role requires strong System Verilog expertise, collaboration across geographies, and a fast ramp on complex IPs in a dynamic environment. Hybrid work model offered in the US.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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