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Sr Principal Engineer, Application Engineering & System Design

Job in Santa Clara, Santa Clara County, California, 95053, USA
Listing for: Fox Point Recruitment LLC
Full Time position
Listed on 2026-08-02
Job specializations:
  • Engineering
    Hardware Engineer, Systems Engineer, Test Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 200000 - 266400 USD Yearly USD 200000.00 266400.00 YEAR
Job Description & How to Apply Below

Job Title:

Senior Principal Engineer, Hardware Application Engineering — Board & System Design

Location: Santa Clara, CA (Onsite — 5 days/week)

Department: Engineering / Architecture

Group: Customer Solutions Group

Position Type: Full-Time (New Position)

Base Compensation: USD $200,000 – $266,400 / year (No variable compensation/bonus flexibility)

Relocation Assistance: Available

Visa Sponsorship: Available

About the Team & Role

Our Customer Solutions Group is the frontline technical partner to the world’s most demanding infrastructure customers—megascale data centers, cloud providers, and AI system builders. We turn cutting-edge silicon into deployable platforms by working shoulder-to-shoulder with customer engineering teams from early architecture through production ramp.

As Senior Principal Engineer for Board & System Hardware Design
, you will serve as the senior technical authority guiding customer hardware design-in on proprietary Ethernet Switch and UALink platforms. You will act as the crucial technical bridge between internal silicon teams, hardware engineering, and field operations.

This is a deep individual contributor role with a strong system-design and productization focus. Your primary mission is to ensure that customers’ next-generation switches, AI fabric platforms, and networking systems are designed right the first time—performant, manufacturable, reliable, and ready for high-volume production.

Technical Leadership & Customer Enablement
System Architecture & Hardware Design Guidance
  • Drive PCB stack-up strategy and material selection (low-loss laminates, copper roughness, glass weave, via construction) to meet high-speed performance and cost targets.
  • Guide customers on power delivery architecture, including PDN design, multi-rail sequencing, decoupling strategy, and tolerance analysis for high-current ASICs.
  • Advise on thermal design, mechanical integration, and cooling strategies (air, liquid, immersion) to meet performance and reliability targets in real deployments.
  • Provide guidance on signal and power integrity (SI/PI), reviewing customer simulations and contributing simulations directly when required.
  • Drive Design for Reliability, Manufacturability, and Testability (DFx)—ensuring smooth transitions to production at ODM/CM partners.
Next-Gen Tech & Cross-Functional Influence
  • Provide technical leadership on 112G and 224G PAM4 Ser Des designs today, and help shape the hardware approach for next-generation 448G systems and open AI fabric standards.
  • Lead hardware bring-up support, root‑cause debug, and issue resolution during customer lab phases and early production.
  • Act as a vital field‑feedback channel to internal silicon and hardware teams—influencing silicon I/O, package, power, and reference design choices based on real‑world customer deployment learnings.
Candidate Profile & Qualifications
Must-Have Requirements
  • Education: Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.
  • Overall

    Experience:

    15+ years in hardware design, development, and validation of high‑speed networking or compute systems.
  • Ser Des Expertise: 7+ years of dedicated experience in board and system design for high‑speed platforms involving modern Ser Des (25G NRZ through 112G/224G PAM4).
  • Board Lifecycle: Proven full‑lifecycle ownership of complex high‑speed boards (architecture, schematic, layout guidance, bring‑up).
  • Reference Designs: Demonstrated experience defining and delivering reference designs that enabled customer or internal platform adoption.
  • Technical Depth:
    • Strong expertise in high‑layer‑count PCB stack‑up design and material selection.
    • Deep experience with power architecture for high‑current ASICs (PDN design, sequencing, decoupling, tolerance analysis).
    • Solid background in thermal design and mechanical integration for high‑power network/AI systems.
    • Working knowledge of SI/PI principles (ability to review and run targeted simulations).
    • Hands‑on lab experience with hardware bring‑up, debugging, and root‑cause analysis using industry‑standard equipment.
    • Deep understanding of high‑speed interfaces:
      Ethernet, PCIe, DDR, advanced Ser Des, and modern power delivery.
  • Soft Skills &…
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