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Senior RTL Design Engineer - RISC-V CPU Microarchitecture
Job in
Santa Clara, Santa Clara County, California, 95053, USA
Listed on 2026-08-07
Listing for:
SiFive, Inc.
Full Time
position Listed on 2026-08-07
Job specializations:
-
Engineering
Hardware Engineer
Job Description & How to Apply Below
SiFive, Inc. is seeking a CPU Microarchitecture/RTL design engineer to join a team creating industry-leading CPU cores based on RISC-V. You will design features, ISA extensions, and optimize performance within the Chisel/FIRRTL workflow.
The role requires 7+ years in CPU RTL design, proficiency in Verilog/System Verilog/VHDL, and strong software engineering skills. Collaboration across teams and a commitment to high-quality hardware are essential.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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