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Senior DFT Architect for AI & HPC ASICs
Job in
Santa Clara, Santa Clara County, California, 95053, USA
Listed on 2026-08-10
Listing for:
Velaura
Full Time
position Listed on 2026-08-10
Job specializations:
-
Engineering
Hardware Engineer, Systems Engineer, Test Engineer
Job Description & How to Apply Below
Velaura is seeking a DFT Architect/Manager/Sr. Manager to define, implement, and execute DFT strategies for AI and HPC silicon.
You will lead test architecture, methodology, and implementation across complex ASIC/SoC designs, collaborating with RTL, verification, physical design, STA, validation, product engineering, and manufacturing teams. You will mentor engineers, drive methodology improvements, and support silicon bring-up, yield ramp, and production quality while staying current with
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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