Power Management Design Engineer

Hardware Engineer

SiFive is looking for hardware engineers who are passionate about designing industry-leading CPU and interconnect IP to help drive the tidal wave of adoption of RISC-V as the architecture of choice for SOC designs across a broad variety of vertical applications. We're creating massively customizable IP and improving time-to-market by designing hardware as highly-configurable generators. We're leveraging technology and ideas from the software industry to execute hardware design with the agility of software development.

As a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU cores and subsystems based on the revolutionary open RISC-V and Tile Link architectures. You will create power management, reset, and clocking solutions that provide the central nervous system for cutting-edge RISC-V CPU and SoC IP designs.

You will work in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance - delivering hardware at the speed of software!

Join us, and surf the RISC-V wave with SiFive!

• Work with the architecture team to understand and define power management requirements.
• Architect, design and implement core clocking, reset and power management solutions.
• Microarchitecture development and specification. Ensure that knowledge is shared via clear documentation and participation in a culture of collaborative design.
• Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.
• Work with a physical implementation team to implement and optimise physical design to meet frequency, area, power goals.
• Work with a software team to enable and optimise power management features.

• 3+ years of recent industry experience in CPU and SoC clocking, reset, and power-management logic designs.
• Experience in high-performance, energy-efficient CPU and SoC designs.
• Expertise in CPU and SoC clocking, reset design, and power management, including:
• Reset control and design strategies:
  Clock distribution, dynamic clocking, clock gating, and clock boundary crossing strategies
• Power state definition and management and Power Management Unit (PMU) design
• Dynamic and static power reduction techniques, including retention and power-up/down sequencing
• Dynamic voltage and frequency scaling (DVFS) and Di/dt mitigation strategies
• Understanding of DFT, MBIST, Debug and Error handling in CPU designs
• Power-aware simulation
• Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL.
• Good understanding of various RTL quality checks like Lint, CDC, RDC etc. Hands-on experience with Spyglass is a plus.
• Attention to detail and a focus on high-quality design.
• Ability to work well with others and a belief that engineering is a team sport.
• Knowledge of at least one object-oriented and/or functional programming language.
• Background of successful CPU or SoC development from architecture through tapeout.
• BS/MS degree in EE, CE, CS or a related technical discipline, or equivalent experience.

• Experience with AMBA Interconnect Protocols, such as AXI, AHB, and APB.
• Experience with AMBA Low Power Protocol Interface, including P-channel and Q-channel protocols.
• Experience with Scala/Chisel, Bluespec, or some other language/DSL for expressing configurable hardware via software
• Knowledge of RISC-V architecture
• Experience with Git/Github, Jira, Confluence