CPU Implementation Lead Engineer
Job in
Santa Clara, Santa Clara County, California, 95053, USA
Listed on 2026-08-12
Listing for:
Apple, Inc.
Full Time
position Listed on 2026-08-12
Job specializations:
-
Engineering
Hardware Engineer, Systems Engineer, Electronics Engineer, Electrical Engineering
Job Description & How to Apply Below
The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products!
Apple's Silicon Engineering Group (SEG) is hiring experienced engineers for the CPU Implementation leadership team.
Description
As a CPU Implementation Lead Engineer, you will own or participate in the following:
CPU IP delivery
Work with multi-functional engineering teams to implement and validate physical design in the aspects of timing, power, area, electrical analysis, functionality, reliability, and testability
Work extensively with the partition implementation team to make area/frequency/performance/power tradeoffs and remove bottlenecks in meeting design targets and delivery schedule
Participate in the definition and enhancement of RTL-to-GDS flow through synthesis and place-and-route targeting aggressive targets for power, performance, and area
Mentor junior engineers
Minimum Qualifications
Minimum BS and 10+ years of relevant industry experience
Experience in driving chip implementation from definition phase to silicon correlation
Experience working with cross-functional teams spanning technology, architecture, RTL & Physical design
Experience in synthesis & place-and-route
Preferred Qualifications
Familiarity with high performance microprocessor architecture fundamentals
Experience in leading initiatives for improving power, performance, & area on CPUs
Knowledge of logic design principles along with timing and power implications
Understanding of low power microarchitecture and implementation techniques
Experience with scripting in Perl and/or TCL
Design experience in deep submicron technologies and basic transistor level design and device physics
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