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Senior CPU RTL Architect & Microarchitecture Lead

Job in Santa Clara, Santa Clara County, California, 95053, USA
Listing for: SiFive
Full Time position
Listed on 2026-08-27
Job specializations:
  • Engineering
Salary/Wage Range or Industry Benchmark: 206000 - 251000 USD Yearly USD 206000.00 251000.00 YEAR
Job Description & How to Apply Below

SiFive in Santa Clara, CA seeks an experienced CPU Microarchitecture/RTL design engineer to help craft industry-leading RISC-V cores. You will work on features, ISA extensions, and performance optimization within a Chisel/FIRRTL framework, collaborating with verification, physical design, and performance teams to deliver high-quality IP.

The role requires a BS/MS in CS/CE/EE, 7+ years of RTL design, Verilog/System Verilog/VHDL proficiency, and strong software engineering skills.

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Position Requirements
10+ Years work experience
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