Principal Wafer Bonding Integration & Packaging Engineer

Principal Wafer Bonding Integration & Packaging Engineer About the Opportunity

Thrively is partnering with a well-funded, rapidly growing deep-tech company developing next-generation semiconductor and photonics technology for high-performance computing and AI infrastructure.

As the company moves from advanced product development toward commercialization and volume manufacturing, we're looking for a Principal Wafer Bonding Integration & Packaging Engineer to take technical ownership of advanced wafer bonding, process integration, packaging development, and manufacturing transfer.

This is a highly cross-functional role at the intersection of wafer process integration, advanced packaging, product engineering, and semiconductor manufacturing. You'll work closely with internal engineering teams and external foundry and manufacturing partners to develop robust bonding and packaging solutions, solve complex integration challenges, and transition new technologies successfully into production.

We're particularly interested in engineers who combine deep technical expertise with a product mindset—people who understand not only how to develop an advanced wafer bonding or packaging process, but how to integrate it into a complete product architecture and make it manufacturable, repeatable, reliable, and scalable.

Candidates with backgrounds in wafer process integration, advanced packaging, MEMS, silicon photonics, heterogeneous integration, 3D integration, or semiconductor technical service engineering are encouraged to apply.

• Own wafer bonding integration strategy from early product development through manufacturing ramp.
• Develop and optimize advanced wafer bonding processes, including:
• Fusion bonding
• Eutectic bonding
• Hybrid bonding
• Direct wafer bonding
• Define and optimize bonding process windows, alignment strategies, thermal budgets, and material compatibility.
• Drive surface preparation, cleaning, activation, CMP requirements, and post-bond processing.
• Develop integration strategies that account for both bonding performance and downstream manufacturing requirements.
• Collaborate with packaging, process integration, and product engineering teams on bonded wafer architectures.

• Partner with design engineering, process development teams, and external manufacturing partners to establish robust manufacturing flows.
• Lead process transfer and qualification activities.
• Drive process readiness for new product introductions.
• Support engineering builds, qualifications, production ramps, and continuous process improvement.
• Ensure bonding processes meet yield, quality, reliability, manufacturability, and schedule requirements.

• Serve as a key technical interface with external semiconductor foundries and fabrication partners.
• Coordinate engineering experiments, process characterization, and process development activities.
• Support tape-outs, process qualifications, and manufacturing ramps.
• Review process data, SPC metrics, excursions, and corrective actions with manufacturing partners.
• Drive improvements in yield, manufacturability, reliability, and cost.

• Analyze wafer-level metrology and inspection data to identify process limitations and failure mechanisms.
• Lead root cause investigations involving bonding defects such as:
• Voids
• Delamination
• Bond strength failures
• Partner with failure analysis teams and external manufacturing partners to implement corrective actions.
• Use DOE, SPC, statistical analysis, and structured problem-solving methodologies to improve process capability and yield.

• BS, MS, or PhD in Materials Science, Mechanical Engineering, Electrical Engineering, Physics, MEMS, or a related technical discipline.
• 10+ years of relevant semiconductor product development, process integration, advanced packaging, or CMOS manufacturing experience.
• Hands‑on product development experience with one or more advanced wafer bonding technologies, such as:
• Fusion bonding
• Eutectic bonding
• Hybrid bonding
• Direct bonding
• Experience with technologies such as TSV integration, wafer thinning,…