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Senior Lead Analog CMOS Layout Engineer
Job in
Santa Clara, Santa Clara County, California, 95053, USA
Listed on 2026-08-30
Listing for:
Sitime-Corporation
Full Time
position Listed on 2026-08-30
Job specializations:
-
Engineering
Electronics Engineer, Systems Engineer
Job Description & How to Apply Below
SiTime is seeking a Senior Layout Design Engineer in Santa Clara, CA to lead top-chip and block- level Analog Layout design for CMOS/BiCMOS circuits. You will coordinate offshore layouts, mentor juniors, and drive standard methodologies to ensure high-quality layouts.
Responsibilities include floor planning, routing, verification (DRC/LVS/ERC), and tape-out support across global teams. Strong Cadence Virtuoso and Calibre skills are required.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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