HSIO Validation Lead – Silicon Co-Design

NVIDIA's accelerated computing platforms move data at speeds that push the limits of what silicon and physics allow. Whether a high-speed interface trains reliably, maintains accurate margins, and survives every platform topology it will ever see is a question we answer ourselves. This role does that work. The Silicon Co-Design Group leads the boundary between what was designed and what was built.

When a GPU, CPU, or SoC ships with interfaces that work at scale, this team is the reason. Most engineers debug within a layer. You will own the full stack. When an interface fails to train, the link margin is unexpectedly tight, or a customer reports a critical silicon issue, you trace the problem through protocol behavior, signal integrity, firmware, platform topology, and silicon marginalities.

You then confirm that the fix works. Your methodology shapes how NVIDIA validates high-speed interfaces across generations. Your decisions affect yield, production ramp, and field quality. This is not a coordination role. The engineers who do it well hold protocol depth and system breadth simultaneously, never lose the thread across hardware, firmware, and software, and have the judgment to know when to go deeper and when to act.

They are rare. Should that describe you, read on.

Own post-silicon bring-up, characterization, validation, and debug of PCIe, NVLink, C2C, and other HSIO interfaces across NVIDIA GPUs, CPUs, and SoCs from first power-on through production readiness. Close the hardest failures. Drive root cause across protocol behavior, signal integrity, firmware and driver interactions, platform topology, and silicon marginalities and own every fix through to confirmation. Define validation strategy. Set test coverage, debug priorities, margining methodology, and stress criteria for each program.

Your strategy is what stands between a silicon risk and a customer escape. Own and build AI agents that operate under your direction. These include automated debug triage, intelligent data pipelines, and analysis flows. They reduce cycle time and identify issues before production. Know where AI accelerates real work and where it introduces risk. Ensure robust interoperability across the full ecosystem: retimers, switches, accelerators, CPUs, GPUs, and sophisticated multi-device system topologies.

Sit at the decision table. Your analysis drives alignment across architecture, logic design, circuit design, firmware, drivers, ATE, DGX, and product teams. Your data is what settles calls. Translate what you learn on real silicon into methodology and coverage improvements that make future products harder to escape.

BS or MS in Electrical Engineering, Computer Engineering, or Systems Engineering, or equivalent experience in the lab. 8+ years in silicon validation, HSIO bring-up, or high-speed interface debug on real hardware. Deep protocol expertise in PCIe, NVLink, CXL, C2C, Ethernet, USB, or similar high-speed interface technologies. Strong signal integrity fundamentals: SERDES behavior, link training, equalization, clocking, reset, power management, and high-speed board and system interactions.

Hands‑on lab depth: oscilloscopes, BERTs, protocol analyzers, logic analyzers, exercisers, and silicon debug tools. The ability to debug across the full stack, hardware, firmware, drivers, and platform design, without losing the thread. Enough statistical proficiency to recognize the moments a marginal distribution is telling you something and enough develop intuition to know where to look next!

Recognized depth in PCIe, NVLink, CXL, or advanced SERDES validation, with failures that other teams brought to you. You've built or deployed AI-driven flows…