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Senior DFT Engineer SoC/ASIC Tapeouts & MBIST
Job in
Santa Clara, Santa Clara County, California, 95053, USA
Listed on 2026-08-30
Listing for:
MosChip Technologies Limited
Full Time
position Listed on 2026-08-30
Job specializations:
-
Engineering
Hardware Engineer, Test Engineer, Electronics Engineer
Job Description & How to Apply Below
Mos Chip Technologies Limited is seeking a Senior DFT Engineer in the Bay Area, CA to support the implementation and verification of DFT solutions across the full flow from scan to silicon bring-up. The role requires hands-on experience with MBIST, JTAG, and Memory Repair, plus strong collaboration with design teams.
Candidates should have 3–8 years of DFT experience, proficiency with Tessent/EDA tools, and scripting in TCL/Perl.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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