Member of Technical Staff - RTL Design

Acceler8 Talent is partnering with an early-stage semiconductor startup developing a new AI inference architecture for large-scale data center deployments.

They’re looking for a Senior/Principal-level engineer to own the architecture and microarchitecture of the data movement subsystem within a next-generation AI accelerator SoC. This is a highly technical, hands-on role with influence from initial architectural definition through tapeout, bring-up, and silicon optimization.

What you’ll work on:

• Architect high-performance data movement pipelines, scheduling mechanisms, and associated control logic
• Define and optimize No
  
  Cs, crossbars, switches, buffers, scratchpad memories, and memory pathways
• Develop microarchitectural solutions balancing throughput, utilization, latency, power, and area
• Use performance models and workload analysis to drive architecture decisions
• Partner closely with compiler, kernel, performance, RTL, and verification engineers
• Explore hardware/software trade-offs around the ISA and programming model
• Support RTL implementation, verification, physical implementation, and timing closure
• Participate in emulation, first-silicon bring-up, performance analysis, and silicon debug

What they’re looking for:

• Deep expertise in NoC architecture, buffering, memory systems, switching/crossbar fabrics, and scheduling
• Proven ownership of complex data movement or memory-related hardware across multiple silicon generations
• Direct experience designing AI accelerators, GPUs, NPUs, or other high-performance compute architectures
• Strong understanding of performance-per-watt and PPA optimization
• Experience taking designs through to working silicon
• Comfort operating across architecture, microarchitecture, and implementation rather than within a narrow functional silo
• Experience in a startup or early-stage silicon environment is a plus
• Typically 5–10+ years of relevant industry experience, with an MS/PhD or equivalent technical background

This is a strong opportunity for someone who wants significant architectural ownership and the chance to influence a new accelerator platform at an early stage.