Technical Manager; Physical Design

• Deliver low power designs using advanced UPF methodologies on 5nm/3nm nodes.
• Resolve SoC/SS integration challenges including SDC constraints and UPF promotion/pushdown.
• Develop and maintain automation flows using Tcl, Python, and Shell.
• Collaborate with cross-functional teams for design closure and signoff.
• Mentor and lead junior team members.
• Innovate and contribute to flow/methodology improvements.

Location
-Santa Clara, CA, USA

Position – Full Time

10+ years

• Drive physical design flow: synthesis, floor planning, placement, CTS, routing, timing closure.
• Deliver low power designs using advanced UPF methodologies on 5nm/3nm nodes.
• Resolve SoC/SS integration challenges including SDC constraints and UPF promotion/pushdown.
• Develop and maintain automation flows using Tcl, Python, and Shell.
• Collaborate with cross-functional teams for design closure and signoff.
• Mentor and lead junior team members.
• Innovate and contribute to flow/methodology improvements.

• Experience in physical design and timing closure.
• Bachelors degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
• Knowledge of RTL2
  
  GDSII flow and design tape-outs in 5nm or below process technologies.
• Experience with EDA tools like DC/Genus, InnovICC2, Primetime, Redhawk/Voltus, or Calibre.
• Hands-on experience in SoC floor planning, place & route, power and clock distribution, and timing convergence of high-frequency designs.
• Knowledge of geometry/process/device technology implications on physical design.
• 10+ years of experience in interpersonal, teamwork, and demonstrated experience communicating and interfacing with cross-functional teams, IP, and EDA vendors.
• Programming/scripting skills: TCL, Python, Perl or Shell.

• 401(k)
• 401(k) matching
• Dental insurance
• Health insurance
• Life insurance
• Paid time off
• Referral program
• Vision insurance
• Short/Long Term Disability