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Senior Memory Subsystem Verification Engineer

Job in Santa Clara, Santa Clara County, California, 95053, USA
Listing for: Nutanix
Full Time position
Listed on 2026-09-02
Job specializations:
  • Engineering
    Test Engineer
Salary/Wage Range or Industry Benchmark: 153000 - 230000 USD Yearly USD 153000.00 230000.00 YEAR
Job Description & How to Apply Below

Qualcomm Technologies, Inc. is seeking a motivated Design Verification Engineer to join its memory subsystem verification team.

You will develop verification strategies, build UVM-based test benches, and drive coverage closure for high-performance memory interfaces (LPDDR/DDR/HBM) and related PHY logic. The role emphasizes hands-on verification with Verilog, System Verilog, UVM, and SVA, spanning the full verification lifecycle from planning to regression and debug.

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Position Requirements
10+ Years work experience
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