PD Engineer

Qualcomm is seeking a PD Engineer to drive physical design implementation for advanced wireless and 5G SoCs. In this role, you will own block- and/or chip-level place-and-route, floor planning, clock-tree synthesis, timing closure, power and IR analysis, and physical verification (DRC/LVS). You will collaborate closely with RTL, architecture, and packaging teams to optimize PPA and ensure robust manufacturability on cutting edge process nodes.

The position offers exposure to next generation mobile, AI, and automotive platforms in a fast paced, innovative environment with strong opportunities for technical growth and global impact.

Responsibilities

• Own block- and chip-level physical design implementation for advanced So
• Cs
• Perform floor planning, place-and-route, and clock-tree synthesis
• Drive static timing analysis and timing closure across PVT corners
• Conduct power, IR drop, and electromigration analysis and optimization
• Run and debug physical verification, including DRC and LVS signoff
• Collaborate with RTL, architecture, and packaging teams to optimize PPASupport design-for-manufacturability and design-for-test requirements
• Contribute to methodology improvements and CAD flow automation
• Review and analyze foundry PDK updates and integrate into flows
• Document design approaches and present status to cross-functional teams

Required Skills

• Physical design (place-and-route)
• Floor planning
• Clock-tree synthesis (CTS)
• Static timing analysis (STA)
• Power and IR drop analysis
• Electromigration analysis
• Physical verification (DRC/LVS)
• Advanced process node design (7nm and below)
• EDA tools (Cadence/Synopsys)
• Scripting (Tcl/Perl/Python)