STA Engineer

Qualcomm is seeking an STA Engineer to drive static timing analysis for advanced wireless SoCs in our Telecommunications & Media portfolio. You will own timing closure for complex digital designs, including constraint development, timing signoff, and path optimization across multiple process, voltage, and temperature corners. Partner with RTL, physical design, and verification teams to debug violations, improve performance, and ensure robust silicon.

Ideal candidates bring strong STA tool expertise, solid understanding of digital design and clocking, and a passion for pushing the limits of high speed, low power wireless technologies.

Responsibilities

• Perform full-chip and block-level static timing analysis for complex wireless So
• Cs
• Develop, validate, and maintain SDC timing constraints across multiple modes and corners
• Collaborate with RTL and physical design teams to debug and resolve timing violations
• Drive timing closure through optimization of logic, placement, and routing
• Support timing signoff, documenting and communicating results to cross-functional stakeholders
• Analyze clocking architecture, skew, and uncertainty to ensure robust design margins
• Automate STA flows, reports, and checks using scripts and EDA tool features
• Partner with verification and implementation teams to balance performance, power, and area
• Contribute to methodology improvements for next-generation 5
• G and connectivity products
• Review design changes for timing impact and provide guidance on best practices

Required Skills

• Static Timing Analysis (STA)
• SDC constraint development
• So
• C and ASIC digital design
• STA tools (Prime
• Time, Tempus or equivalent)
• Clock tree and timing closure
• Multi-corner, multi-mode analysis
• Scripting (Tcl, Python, or Perl)
• Low-power design techniques
• Physical design interaction (placement, routing)
• Timing signoff methodologies