Senior Physical Design Engineer

Senior Physical Design Engineer

At Capgemini Engineering, we bring together a global team of engineers, scientists, and architects to help the world's most innovative companies unleash their potential. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.

Location:

This is an onsite role based in Santa Clara, CA.

As a Physical Design Engineer, you will work on complex digital and mixed-signal designs across advanced process technologies, helping drive designs from implementation through verification and tape-out. This role offers the opportunity to solve challenging physical design problems, collaborate with cross-functional engineering teams, and support next-generation IC product development using industry-leading methodologies and tools.

As a Physical Design Engineer, you will support the implementation and optimization of advanced-node semiconductor designs. Key responsibilities may include:

• Lead or support physical design activities, including floor planning, placement, clock tree synthesis, routing, and physical-aware synthesis.
• Develop and implement power-grid strategies, high-speed clock constraints, and design specifications to support performance, power, and area goals.
• Perform physical design verification and debug LVS and DRC issues at both chip and block levels.
• Collaborate with design, layout, verification, timing, and methodology teams to address implementation challenges across the design lifecycle.
• Support CDC, static timing analysis, parasitic-aware simulation, and timing closure activities using relevant EDA tools and methodologies.
• Contribute to tape-out readiness, including design signoff, foundry interaction, and alignment with IC product development requirements.
• Evaluate design tradeoffs related to power consumption, area, performance, layout complexity, and technology limitations for advanced process nodes(3nm /5nm/7nm)

We are looking for candidates with strong physical design expertise and hands-on experience in advanced semiconductor implementation. Ideal qualifications include:

• 10+ years of Physical Design experience with hands-on expertise supporting complex digital and mixed-signal IC implementation.
• Strong knowledge of the complete physical design flow, including floor planning, placement, clock tree synthesis (CTS), place-and-route (P&R), physical-aware synthesis, timing closure, and design signoff.
• Deep understanding of industry-standard physical design methodologies and best practices related to floor planning, CTS, routing, optimization, and design closure.
• Proven experience developing and implementing power-grid architectures, high-speed clock constraints, and design specifications to achieve aggressive power, performance, and area (PPA) goals.
• Strong expertise in Static Timing Analysis (STA), including timing closure, parasitic delay analysis, and optimization across multiple operating modes and process-voltage-temperature (PVT) corners.
• Experience with Clock Domain Crossing (CDC) analysis, methodologies, verification tools, and timing signoff processes.
• Hands-on experience performing physical verification and signoff, including debugging and resolving DRC, LVS, and other physical signoff violations at both chip and block levels.
• Solid understanding of mixed-signal design environments and the interaction between digital implementation and analog/layout requirements.
• Experience supporting tape-out readiness, foundry signoff, and semiconductor product development life cycles for advanced-node designs.
• Strong understanding of PPA tradeoffs, power integrity, and advanced-node implementation challenges.
• Hands-on experience with industry-standard EDA tools, including Cadence Innovus, Quantus, Voltus, Calibre, Red Hawk, and equivalent implementation, timing, and signoff platforms.
• Experience with advanced TSMC process technologies (7nm, 5nm, 3nm and below)

Preferred

Skills:

• Experience estimating design and layout effort for digital blocks in advanced-node technologies.
• Strong understanding of power, performance, and area tradeoffs in leading-edge process technologies.
• Prior experience supporting full-chip or block-level tape-out to foundries.
• Ability to work collaboratively across multiple engineering disciplines and communicate technical tradeoffs clearly.

The base compensation range for this role in the posted location is: $82,082 to $193,440. Capgemini provides compensation range information in accordance with applicable national, state, provincial, and local pay transparency laws. The base compensation range listed for this position reflects the minimum and maximum target compensation Capgemini, in good faith, believes it may pay for the role at the time of this posting.

This range may be subject to change as permitted by law. The actual compensation offered to any candidate may fall outside of the posted range and will be determined based on multiple factors legally permitted in the…