DFT Engineer

We are seeking a Senior DFT Engineer with 8–12 years of relevant experience in DFT Scan Insertion and ATPG Validation
. The ideal candidate will have strong hands‑on experience with industry‑standard DFT methodologies, scan architecture, ATPG flows, and DFT implementation.

The candidate should have practical experience working with Mentor Tessent (Siemens) and Synopsys DFT Compiler
, along with a strong understanding of scan insertion, ATPG generation, validation, debugging, and DFT‑related issues.

Duration: 12 Months

Experience: 8–12 Years

• Perform DFT Scan Insertion and support scan architecture implementation.
• Develop, execute, and validate ATPG flows and test patterns
  .
• Analyze and debug ATPG and DFT‑related issues.
• Work with design and verification teams to resolve scan and testability issues.
• Support DFT implementation, validation, and sign‑off activities.
• Apply industry‑standard DFT methodologies throughout the ASIC/SoC design flow.

• 8–12 years of hands‑on DFT engineering experience
  .
• Strong experience in DFT Scan Insertion
  .
• Hands‑on experience with ATPG Validation
  .
• Strong understanding of DFT methodologies, scan architecture, and ATPG flows
  .
• Strong debugging and problem‑solving skills.