Hardware Design Engineer

CT Server DDR Team Position

As a member of the CT Server DDR team, we are looking for an experienced signal integrity and power integrity engineer who can be responsible for DDR PHY channel and power delivery network (PDN) architecture, system-level SI/PI, and post-silicon validation.

The engineer needs to be hands-on in defining channel and PDN architectures, modeling signal and power delivery at the system level, and validating SI/PI on silicon. The engineer needs to work with design, package, board, and firmware teams on the specification of SI/PI targets and their implementation, and to help debug issues across the full system stack.

Key responsibilities include running system-level channel and PDN simulations (insertion/return loss, crosstalk, eye diagrams, impedance, IR drop, jitter transfer) and correlating with silicon results. The engineer should be able to process post-silicon SI/PI validation data and drive the next steps, debug SI/PI issues across silicon, package, and board, working with firmware and design teams, and support cross-functional teams with system, channel, PDN, and decoupling implementation details.

Preferred experience includes strong coding skills in Python and Matlab, signal integrity (SI) and power integrity (PI) knowledge, including S-parameter/Z-parameter analysis, channel modeling, and PDN modeling, knowledge of Ansys or Cadence simulation tools (e.g., HFSS, SIwave, Sigrity, Clarity), system-level experience with firmware and hardware debug expertise, and system modeling with silicon-to-simulation correlation. Firmware development for ATE and platforms is also preferred.

Academic credentials should include a bachelors or masters degree in Computer Engineering/Electrical Engineering.

Location:

Santa Clara, CA (open to other locations)