Principal Design Verification Engineer – CPU Core Hardware Prefetch

SiFive is looking for a Principal Design Verification Engineer to lead verification strategy and execution for CPU Core Hardware Prefetch in a high‑performance out‑of‑order core.

This senior tech‑lead role will define architecture‑aware verification strategy, identify microarchitectural risk early, solve the most challenging hardware prefetch verification problems, and raise verification quality across the broader CPU DV organization.

The primary technical scope of this role is advanced hardware prefetch verification, with emphasis on prefetch training behavior, stream detection and replacement, request generation, issue‑queue behavior, DCache interactions, feedback‑driven aggressiveness control, CSR configurability, and functional correctness across block‑level and core‑level integration contexts.

Collaborating closely with architecture, RTL, performance, software, and verification teams, the engineer will ensure design intent is captured correctly, risks are identified early, and sign‑off quality is achieved with strong technical judgment and scalable methodology.

• Lead verification planning and execution for CPU hardware prefetch functionality in a high‑performance out‑of‑order core, spanning unit‑level and core‑level strategy, debug, coverage closure, and sign‑off readiness.
• Define verification strategy, test plans, checkers, scoreboards, assertions, stimulus strategies, and coverage models for advanced hardware prefetch microarchitecture and its corner cases.
• Drive verification of hardware prefetch behaviors including stream allocation and replacement, training from demand requests, prefetch generation, request replay and kill behavior, issue‑queue interactions, and feedback‑driven control of prefetch aggressiveness.
• Verify correctness of runtime configurability through hardware prefetch CSRs, including enablement, windowing, initial distance, maximum allowed distance, linear‑to‑exponential growth thresholds, queue‑allocation controls, and thresholds tied to L1/L2 cache and MSHR behavior.
• Drive verification of interactions between the hardware prefetch engine and the memory hierarchy, including DCache pipeline behavior, cacheable‑read‑only training conditions, MSHR fullness back pressure, L1/L2 prefetch targeting, and arbitration with other core‑generated traffic.
• Develop verification strategies for difficult corner cases such as stream misconfirmation and untraining, queue unavailability, threshold‑triggered throttling, page‑boundary behavior, multi‑stream behavior, and correctness under diverse operating modes and software‑programmed configurations.
• Use architectural counters, self‑checking tests, and microarchitectural observability to validate that prefetch behavior is both functionally correct and robust across realistic performance‑sensitive traffic patterns.
• Partner with architects and designers from early feature‑definition stages to review specifications, identify ambiguity, improve debugability, and influence the design from a verification perspective.
• Apply the right verification method for the problem, including simulation, formal techniques, emulation, and performance‑oriented validation where appropriate for high‑risk or hard‑to‑observe hardware prefetch behaviors.
• Drive efficient failure analysis and root‑cause debug across specification, RTL, test content, assertions, and verification infrastructure.
• Mentor engineers across the organization and shape reusable verification approaches, infrastructure, and methodology for future CPU core generations.

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 12+ years of relevant experience in CPU/core or SoC functional verification, with substantial…