Chip Lead, Silicon Co-Design Group

The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our work spans early architecture through final product delivery across Datacenter, Gaming, Robotics, Automotive, and Embedded markets. We work closely across functions to deliver chips that change what is possible.

NVIDIA’s Silicon Co-Design Group is hiring a Chip Lead to serve as the technical lead for one of our most consequential silicon programs! This is not project management, and it is not a senior IC role. You are the person the program partners with on its hardest technical questions — when the right answer is not obvious, and when leadership needs a single technical perspective to align on direction.

You are accountable for the technical integrity of the chip end-to-end. You guide co-design feature integration, help resolve the toughest multi-functional bugs, and serve as the project-specific custodian of the qualification playbook. The program runs cleaner because you are on it!

You will partner across design, validation, software, and manufacturing to keep the program’s technical narrative clear and on track. Day to day, you will:

• Serve as the single technical point of contact for multi‑functional decisions, issues, and trade‑offs.
• Co‑lead program‑level feature integration from chip to system, surfacing inter‑function dependencies and guiding them to resolution.
• Help resolve the program’s hardest multi‑functional bugs by translating ambiguous, multi‑team symptoms into root‑cause closure on areas such as HBM, power and thermal, high‑speed I/O, and packaging.
• Steward the qualification playbook. When the playbook does not fit a situation, guide the mitigations and capture the lessons as reusable methodology for other SSG programs.
• Shape the program’s technical narrative by surfacing key risks, trade‑offs, and mitigations as decision‑ready options for executive leadership.
• Mentor Chip Leads on adjacent silicon programs and contribute to SCG‑wide methodology through post‑mortems and write‑ups.
• Lead the program’s Critical Debug and SCG Technical Execution forums, and represent the chip externally with early insight into technical risks.

• BS or MS (or equivalent experience) in Electrical or Computer Engineering, plus over a decade of proven track record in post‑silicon bring‑up, validation, or system integration leadership at a major semiconductor company, including work on multiple shipped silicon products.
• 12+ years of experience.
• Strong end‑to‑end understanding of SoC and ASIC architecture, with recognized expertise in at least one subsystem such as HBM, Ser Des, power and thermal, or packaging.
• Specific examples of silicon‑level impact, such as faster bring‑up, fewer escapes, yield recovery, or methodology contributions — especially turning ambiguous, multi‑team failure modes into root‑cause closure with reusable workarounds and write‑ups.
• A track record of guiding technical decisions across functional boundaries without direct reporting authority, and translating sophisticated silicon issues into clear options for executive audiences.

• Prior experience as a Chip Lead, Project Tech Lead, or Principal or Distinguished Engineer on a flagship GPU, AI accelerator, CPU, networking ASIC, or other large SoC. Patents, conference papers, invited talks, or recognized contributions to silicon validation, post‑silicon debug, or co‑design integration are a plus.
• A history of building and sharing technical methodology beyond a single program — reusable playbooks, debug frameworks, or standards adopted by other teams. Hands‑on debug experience with HBM, high‑speed I/O, power and thermal, or packaging is welcome.
• Comfort working through ambiguity with globally distributed teams, and a habit of surfacing the right risks and recommendations to leadership without being asked. Bonus points for using AI tools to lift team velocity, not just personal productivity.

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