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PhD Intern: Analog & Mixed-Signal IC Design
Job in
Santa Clara, Santa Clara County, California, 95053, USA
Listed on 2026-09-09
Listing for:
Jobtailor
Apprenticeship/Internship
position Listed on 2026-09-09
Job specializations:
-
Engineering
Electronics Engineer
Job Description & How to Apply Below
Jobtailor in Santa Clara, CA invites a PhD student in Electrical Engineering to join our analog/mixed-signal design team. Design, simulate, and verify blocks across the full design flow—from architecture and schematic to silicon bring‑up—in advanced CMOS FinFET processes.
Use Cadence and MATLAB for simulation; collaborate with layout engineers; participate in design reviews; and present results. You will also follow a structured analog design curriculum alongside other PhD interns.
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