STA Engineer

Qualcomm Atheros, Inc.

General

Summary:

Qualcomm‑Atheros, a.k.a. QCA () is a wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for the mobile, networking, computing and consumer electronics markets. As a key member of a fast‑paced Integrated Wireless Technology team, the role involves ownership and leading Static timing closure and synthesis for complex low‑power WiFi SoCs and sub‑systems.

• Timing Analysis:
  • Drive subsystem‑level STA and timing closure for both pre‑layout and post‑layout phases, with support at full‑chip level.
  • Perform timing analysis using Prime Time (or equivalent tools) and contribute to full‑chip signoff activities.
  • Identify timing bottlenecks, debug violations, and recommend micro‑architectural or implementation‑level optimizations.
  • Develop and validate SDC constraints, including Multi‑mode and multi‑corner (MMMC) setup, to enable accurate and efficient STA analysis.
  • Define and manage I/O timing budgets across hierarchical designs.
  • Provide actionable timing feedback at block/HM, sub‑system and full‑chip levels, including root cause analysis and ECO guidance.
  • Manage large‑scale multi‑corner/multi‑mode STA runs with automation, partitioning, and efficient resource usage.
  • Collaborate with RTL, synthesis, and physical design teams to ensure robust timing closure.
• Synthesis & Implementation:
  • Perform synthesis (including low power), formal verification (LEC), and low‑power checks for complex SoCs, sub‑systems, and cores.
  • Validate synthesis QoR and ensure clean handoff to physical design.
  • Develop, validate, and maintain SDC constraints.
  • Balance Power, Performance, and Area (PPA) constraints during implementation.
  • Perform functional ECOs including conformal ECOs.
• Methodology:
  • Develop AI‑driven flows using TCL, Perl, and Python scripts to automate and enhance efficiency across STA, synthesis, timing‑constraint development, ECO implementation, and low‑power verification flows.

• 6–8 years of experience in ASIC/SoC STA, synthesis (including low power), timing constraint development, low‑power checks and functional ECO implementation.
• Deep knowledge of Static Timing Analysis (STA) and timing constraints.
• Experience with Multi Mode Multi Corner (MMMC) timing closure, OCV/AOCV/POCV, and advanced technology nodes.
• Experience with timing closure sign‑off requirements.
• Experience in synthesis, logical equivalence checking (LEC) (RTL‑to‑Netlist and Netlist‑to‑Netlist).
• Understanding of SOC clocking and reset methodology and implementation.
• Scripting skills in TCL and Perl.
• Exposure to low‑implementation techniques and design checks (multi‑voltage designs, UPF).
• Hands‑on experience with:
  • Synopsys Prime Time
  • Synopsys Design Compiler / Cadence Genus

• Implementation of Functional ECOs using Conformal ECO Tool.
• Familiarity with low‑power design, bus implementation (AXI/AHB) and clock domain crossing (CDC).
• Exposure to physical design flows.
• Scripting skills using Python.
• Exposure to power estimation using Prime Power (PTPX).
• Familiarity with Wi‑Fi, Bluetooth, or other wireless SoC design.
• Familiarity with peripheral interfaces (PCIe, USB).

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

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