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CPU Clock Design Engineer – Jitter, CTS & Low-Power Timing
Job in
Santa Clara, Santa Clara County, California, 95053, USA
Listed on 2026-09-09
Listing for:
Qualcomm
Full Time
position Listed on 2026-09-09
Job specializations:
-
Engineering
Hardware Engineer, Systems Engineer, Electronics Engineer, Engineering Design & Technologists
Job Description & How to Apply Below
Qualcomm in Santa Clara, CA is seeking a Physical Design Clock Engineer to collaborate with microarchitecture, RTL, CAD, block and top-level physical design teams to create best-in-class clocking solutions for next generation CPUs.
The role requires expertise in clock generation, jitter analysis, and low-skew/low-power design, with responsibilities spanning PLLs, CTS, and clock distribution methodology across CPU designs.
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