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Analog Design Engineer

Job in Santa Clara, Santa Clara County, California, 95053, USA
Listing for: TekWissen ®
Full Time position
Listed on 2026-09-14
Job specializations:
  • Engineering
    Electronics Engineer, Electrical Engineering, Systems Engineer
Salary/Wage Range or Industry Benchmark: 45 - 61 USD Hourly USD 45.00 61.00 HOUR
Job Description & How to Apply Below

Tek Wissen is a global workforce management provider headquartered in Ann Arbor, Michigan that offers strategic talent solutions to our clients world-wide.

Job Title:

Analog Design Engineer Duration: 24 months

Work Type:
Contract Job Type: Onsite Pay Rate: $53.00 - $53.00/HrJOB Description THE PERSON:
  • Solid knowledge Analog Circuit Design in FinFET technology specifically in PLLs and associated subblocks including VCO, charge-pump, dividers, state machines, LDO, feedback and compensation techniques, bandgap, TDC, interpolator circuits, high speed buffers etc.
  • Solid knowledge of industry standard tools and practices for analog circuit design
  • Good knowledge in Physical design, STA, methodology scripts (Tcl), knowledge on Perl, Python
  • Quality-oriented mindset
  • Strong and effective communication skills and team spirit
Key Responsibilities
  • Help design of building blocks of a PLL
  • Run pre-tapeout verification flows to confirm design meets performance, power, reliability and timing requirements.
  • Work closely with layout engineers to deliver the physical design as well as define production/bench-level test plans with post-silicon characterization groups for silicon evaluation to ensure interlocked and high-quality execution
Preferred Experience
  • 3-5 years of professional experience in the semiconductor industry
  • Experience in FinFET & Dual Patterning nodes such as 16/14/10/7nm/5nm
  • Hands-on design experience in performance analog and hybrid Phase Locked Loops, analog-to-digital (ADC), digital-to-analog (DAC) data converter, VCO, LDO, bandgap, charge pump, op-amps, interpolator circuits.
  • Experience with the following is a plus:
    Digital PLL techniques, TDC or DSP and control theory experience related to digital PLLs, Dual charge-pump PLL designs, Fractional-N PLLs, spread-spectrum PLLs.
  • Proficient with Cadence custom circuit design tools like ADE-L and ADE-XL and running Monte-Carlo, noise, aging, EM and IR drop simulations and stability analysis. Helic/EMX is a plus.
  • Have good experience with simulation tools such as Spectre, Hspice, AFS, and MATLAB, System Verilog, Python.
  • Capable of understanding DRC and LVS results with verification tools (Calibre, ICV, or like)
  • Proficiency in scripting languages like Perl, Python, matlab etc. is a plus.
  • Able to work effectively in a team, with good interpersonal skills, enthusiasm and positive energy
  • Possess strong analytical/problem solving skills and pronounced attention to details
  • Must be a self-starter, and able to independently drive tasks to completion
Academic Credentials
  • Master s or Bachelor's degree in electrical engineering or equivalent required

Tek Wissen Group is an equal opportunity employer supporting workforce diversity.

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