ASIC Emulation Engineer

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MTS SILICON DESIGN ENGINEER 

THE ROLE:

AMD’s Network Technologies Solutions Group (NTSG) develops advanced networking silicon and software for data center, cloud, and enterprise infrastructure.

We are seeking a hands-on MTS ASIC Emulation Engineer to lead emulation of complex networking subsystems and SoCs using ZeBu, Veloce, and Palladium platforms. You will define emulation strategy, build scalable environments, enable hardware-software co-verification, and drive functional and performance validation before silicon.

You will work on next-generation technologies spanning high-speed Ethernet, PCIe, DMA, RDMA, packet processing, traffic management, embedded processors, firmware, and complete system use cases.

THE PERSON:  The ideal candidate combines deep ASIC knowledge with strong emulation, debug, and software skills. You can take a large design from RTL handoff through compilation, bring-up, workload enablement, regression, performance analysis, and verification closure.

You are equally comfortable debugging RTL, transactors, test environments, firmware, software, and system interactions. You remain hands-on while providing technical leadership, improving methodology, and coordinating across architecture, design, DV, firmware, software, FPGA, and silicon-validation teams.

KEY RESPONSIBILITIES Emulation Architecture & Platform Bring-UpDefine emulation strategy for complex networking IP, subsystems, and SoCs.Bring up and deploy designs on ZeBu, Veloce, Palladium, or equivalent platforms.

Develop reusable emulation environments, transactors, and infrastructure.

Drive platform readiness, scalability, stability, and validation closure.

Hardware-Software Co-Verification Enable firmware boot, driver development, operating-system bring-up, and system-level workloads prior to silicon.

Develop and execute end-to-end validation scenarios spanning hardware, firmware, and software.

Partner closely with firmware and software teams to accelerate product development and debug.

Networking & Performance Validation Validate networking and I/O subsystems including Ethernet, PCIe, DMA, RDMA, packet processing, and traffic management.

Execute long-running workloads and use cases that are impractical in RTL simulation.

Verify throughput, latency, QoS, congestion, and system-level performance against architectural goals.

Execution, Debug & Leadership Debug complex issues across RTL, emulation infrastructure, firmware, drivers, and software stacks.

Drive workload enablement, regression health, failure triage, and validation closure.

Collaborate with architecture, design, verification, and silicon-validation teams.

Mentor engineers and provide technical leadership across emulation activities.

LANGUAGES & TOOLS Required

Strong hands-on experience with ZeBu, Veloce, Palladium, or equivalent hardware emulation platforms.

Strong debug skills spanning RTL, firmware, software, and system-level interactions.

Experience with transactors, emulation environments, and hardware-software co-verification.

Proficiency in C/C++, Python, Tcl, Shell, or equivalent scripting languages.

Preferred Experience with high-speed Ethernet, RDMA/RoCE, PCIe Gen5/Gen6, or advanced networking architectures.

Experience with pac…