Senior Manager, Silicon Speed Productization — Silicon Co-Design Group

NVIDIA’s Silicon Co-Design Group (SCG) sees every silicon program from first power-on to high-volume production. We sit at the intersection of architecture, design, marketing, operations, and productization, turning silicon behavior into products that deliver industry-defining performance, power efficieresolvency, yield, and quality. We are hiring a Senior Manager to lead our Silicon Speed Productization team. In this role you will own simulation-to-silicon speed correlation and determine whether each product delivers its intended frequency across voltage, process, temperature, workload, and lifetime conditions.

This is not a coordination role or a validation-only role. You and your team will identify where predictions diverge from measured silicon, drive the hardest issues to root-cause closure, and establish the technical basis for product limits, guard bands, binning, and production sign-off!

Your organization will lead senior individual contributors and a first-line manager at the boundary between what was designed and what was built. Architecture, design, product, and senior leaders will use your data and judgment to make program decisions. Success in this role means that speed risks are raised early, correlation improves with every generation, and programs ship at speed-of-light schedules. The exceptional leader also applies AI deliberately—with demonstrated workflow impact!

What you’ll be doing :

Close the prediction-to-silicon loop:
Own speed characterization and correlation from pre-silicon planning and first power-on through production sign-off across GPU, CPU, and SoC programs

Resolve the hardest speed failures:
Drive root-cause closure when a frequency corner does not hold, minimum operating voltage is too high, a critical path escapes timing analysis, or workload behavior diverges from the model

Define product limits with evidence:
Refine methodologies for silicon margining, process-voltage-temperature characterization, guard banding, aging, and speed binning, and translate the results into product requirements and production decisions

Left-shift learning:
Feed measured-silicon insights back into timing models, critical-path predictions, test content, design practices, and future architectures so that each program begins with a stronger correlation baseline

Give leadership the clarity to act:
Convert characterization data, model deltas, yield trends, and program risks into crisp, decision-ready options for leadership on plan-of-record, qualification, production, and ramp decisions

Scale analysis and coverage:
Build closed-loop data, automation, and AI-assisted workflows for test orchestration, anomaly detection, triage, and reporting that improve coverage and cycle time Build the organization NVIDIA depends on:
Hire, develop, and retain a high-performing, globally-distributed team; grow engineers into recognized subsystem experts and develop first-line managers into independent leaders

What we need to see:

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Systems Engineering (or equivalent experience)12+ overall years of experience in silicon characterization, post-silicon validation, timing or performance analysis, including 5+ years leading technical teams

Proven management experience developing senior engineers and first-line managers

Deep technical foundation in digital design, computer architecture, static timing analysis, critical-path behavior, clocking, power and timing interactions, semiconductor process variation, sampling, and statistics.

Hands-on expertise with silicon speed characterization, simulation-to-silicon correlation, voltage-frequency margining, guard banding, and process-voltage-temperature and binning dependencies for high-performance silicon

Demon…