Senior Implementation Methodology Engineer

Role Overview

We want a skilled and motivated Implementation Methodology Engineer for NVIDIA's elite VLSI team. This role involves owning synthesis methodology development in the RTL2

GDS pipeline and supporting advanced-node chip development, leading aggressive PPA optimization campaigns and inventing next-generation efficiency automation to multiply engineering throughput across build teams.

• Own and continuously improve the end-to-end RTL2
  
  GDS implementation methodology—including synthesis, place & route, CTS, and equivalence checking—for advanced-node CPU builds.
• Evaluate new EDA tools and process node capabilities; deliver clear adoption recommendations.
• Act as the technical liaison between internal teams and EDA vendors (Synopsys, Cadence) to resolve tool issues and influence vendor roadmaps.
• Define and enforce implementation methodology best‑practice knowledge metrics (BKMs) and flow standards across development teams; maintain user documentation and lead training on tools and flows.
• Build and complete rigorous A/B and multi-variant experiments to quantitatively compare flows, engine settings, and optimization strategies for QoR impact.
• Drive aggressive PPA targets throughout the full implementation cycle.
• Conduct deep root‑cause analysis on timing closure bottlenecks, power limiters, and long‑tail QoR issues; develop methodologies to resolve these problems at scale.
• Architect and build Python/TCL/Perl automation frameworks that reduce manual engineering effort and improve design turnaround time across implementation teams.
• Identify systemic efficiency bottlenecks across the implementation flow and eliminate them through targeted automation, data‑driven regression infrastructure, and AI/ML‑assisted flow optimization.
• Partner with architecture, RTL, DFT, physical build, and sign‑off teams to surface PPA opportunities early and translate methodology improvements into measurable silicon impact.

• BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent experience.
• 6+ years of hands‑on proven experience in ASIC implementation methodology and EDA tool/flow development.
• Deep, practical expertise in the complete RTL2
  
  GDS flow: synthesis, DFT, floor planning, placement, CTS, routing, and MCMM STA.
• Power user of synthesis and place‑and‑route tools from Synopsys (DC/FC, ICC2, Prime Time) and/or Cadence (Genus, Innovus, Tempus).
• Prior experience in data‑focused EDA tool evaluation, flow benchmarking, and methodology development with demonstrated PPA impact.
• Strong scripting proficiency in Python, TCL, Perl, and/or Make for flow automation and analysis.
• Demonstrated ability to drive complex, cross‑functional technical initiatives—aligning build, CAD, and EDA vendor teams toward shared goals.
• Excellent problem‑solving, debugging, and analytical skills with a track record of simplifying complex, cluttered environments.
• Strong interpersonal and communication skills; able to translate technical findings into actionable recommendations for diverse audiences.

• Demonstrated application of AI/ML or GenAI techniques to physical build, QoR analysis, flow automation, or design space exploration— in production or research contexts.
• Solid understanding of front‑end flows and methodology: RTL build intent, DFT insertion, synthesis constraints, and UPF/CPF low‑power build—enabling an end‑to‑end perspective.

Competitive salaries and a comprehensive benefits package. The base salary range is 168,000 USD to 264,500 USD. You will also be eligible for equity and benefits. Hiring and promotion practices are nondiscriminatory. NVIDIA is a committed equal‑opportunity employer.

NVIDIA is committed to fostering an inclusive work environment and is proud to be an equal opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.