Principal Ethernet Scale-Out Architect, AI Data Center

Job Title

Hardware Scale-Out Architect

Qualcomm is seeking an experienced Hardware Scale-Out Architect to help define the next generation of AI datacenter products. This role is responsible for architecting large-scale Ethernet-based AI/datacenter fabrics that connect servers, accelerators, racks, and multi-rack clusters. The ideal candidate will bring deep expertise across Ethernet, UEC, RoCE/RDMA, NICs/SuperNICs, scale-out switches, scale-up interconnects, and end-to-end system data movement.

The selected candidate will drive system architecture and requirements from the accelerator card and server level through rack and cluster-scale deployments, partnering closely with SoC, software, card, platform, and product teams.

• Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.

• 8+ years of hardware architecture, design, validation, testing, or commercialization experience in datacenter, networking, accelerator, or high-speed I/O products.
• Strong understanding of Ethernet, Infini Band, RoCEv2, RDMA, and related transport protocols.
• Ability to work closely with software teams to optimize end-to-end data movement for high bandwidth, low latency, and efficient resource utilization.
• 3+ years of experience with datacenter products such as servers, accelerators, NICs, switches, racks, or cluster-scale systems.
• Strong knowledge of scale-out networking and scale-up interconnect architectures for AI and cloud infrastructure.
• In-depth knowledge of Ethernet, high-speed Ser Des, PCIe/CXL-class interfaces, and board/system-level connectivity tradeoffs.
• Strong understanding of telemetry, observability, RAS, reliability, error handling, and failure-mode analysis in large-scale systems.
• Strong understanding of security, isolation, virtualization, and multi-tenant deployment requirements in datacenter environments.
• Strong understanding of DMA engines, memory hierarchy, I/O virtualization, and accelerator data-movement architectures.
• Ability to operate effectively in a high-caliber, cross-functional, international, and multi-site engineering environment.

• Good understanding of PCIe, CXL, and UCIe protocols and their use in accelerator, server, and rack-scale architectures.
• Familiarity with Ethernet switch management and control-plane ecosystems such as SONiC, SAI, OpenBMC, Linux networking, and related platform software.
• Good understanding of high-speed Ser Des and Ethernet PHY design considerations, including signal integrity, reach, power, latency, and platform tradeoffs.
• Ability to work with customers, product management, architecture, and engineering teams to gather requirements and translate them into clear technical specifications.

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The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation  also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus).

In addition, our highly competitive benefits package is designed to support your success at work, at home, and r recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.