Principal Ethernet Scale-Out Architect, AI Data Center

Company:

Qualcomm Technologies, Inc.

Engineering Group, Engineering Group > ASICS Engineering

Qualcomm is seeking an experienced Hardware Scale-Out Architect to help define the next generation of AI datacenter products. This role is responsible for architecting large-scale Ethernet-based AI/datacenter fabrics that connect servers, accelerators, racks, and multi‑rack clusters. The ideal candidate will bring deep expertise across Ethernet, UEC, RoCE/RDMA, NICs/SuperNICs, scale‑out switches, scale‑up interconnects, and end‑to‑end system data movement.

• Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
• OR
• Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
• OR
• PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.

• Define next‑generation scale‑out network architectures for AI and cloud datacenter deployments.
• Develop end‑to‑end system architecture spanning accelerator cards, servers, racks, and multi‑rack clusters.
• Drive architecture and requirements for Ethernet fabrics, NICs/SuperNICs, switch ASICs, transport protocols, in‑network collectives, telemetry, security, virtualization, RAS, and reliability features.
• Analyze DMA engines, data flows, packet flows, and system bottlenecks to optimize bandwidth, latency, utilization, and scalability.
• Collaborate with software, SoC design, card design, platform, and validation teams to realize connectivity solutions for AI scale‑up and scale‑out deployments.
• Provide technical leadership across physical, link, transaction, transport, and protocol layers of high‑speed interfaces and datacenter networking systems.

• 8+ years of hardware architecture, design, validation, testing, or commercialization experience in datacenter, networking, accelerator, or high‑speed I/O products.
• Strong understanding of Ethernet, Infini Band, RoCEv2, RDMA, and related transport protocols.
• Ability to work closely with software teams to optimize end‑to‑end data movement for high bandwidth, low latency, and efficient resource utilization.
• 3+ years of experience with datacenter products such as servers, accelerators, NICs, switches, racks, or cluster‑scale systems.
• Strong knowledge of scale‑out networking and scale‑up interconnect architectures for AI and cloud infrastructure.
• In‑depth knowledge of Ethernet, high‑speed Ser Des, PCIe/CXL‑class interfaces, and board/system‑level connectivity tradeoffs.
• Strong understanding of telemetry, observability, RAS, reliability, error handling, and failure‑mode analysis in large‑scale systems.
• Strong understanding of security, isolation, virtualization, and multi‑tenant deployment requirements in datacenter environments.
• Strong understanding of DMA engines, memory hierarchy, I/O virtualization, and accelerator data‑movement architectures.
• Ability to operate effectively in a high‑caliber, cross‑functional, international, and multi‑site engineering environment.

• Good understanding of PCIe, CXL, and UCIe protocols and their use in accelerator, server, and rack‑scale architectures.
• Familiarity with Ethernet switch management and control‑plane ecosystems such as SONiC, SAI, OpenBMC, Linux networking, and related platform software.
• Good understanding of high‑speed Ser Des and Ethernet PHY design considerations, including signal integrity, reach, power, latency, and platform tradeoffs.
• Ability to work with customers, product management, architecture, and engineering teams to…