Principal Design Verification Engineer – CPU Core Frontend

About the Role

SiFive is looking for a Principal Design Verification Engineer to lead verification strategy and execution for the CPU Core Frontend in a high-performance out-of-order core. This is a senior tech-lead role for an engineer who can define architecture-aware verification strategy, identify microarchitectural risk early, solve the hardest frontend verification problems, and raise verification quality across the broader CPU DV organization.

The primary technical scope of this role is frontend verification, with emphasis on branch prediction, instruction fetch, frontend redirects and recovery, prediction training/update behavior, fetch correctness, and interface interactions across the frontend pipeline. The role requires close partnership with architecture, RTL, performance, and verification teams to ensure design intent is captured correctly and signoff quality is achieved with strong technical judgment and scalable methodology.

• Lead verification planning and execution for CPU frontend functionality in a high-performance out-of-order core, with ownership spanning branch prediction and instruction fetch behavior.
• Define verification strategy, test plans, checkers, scoreboards, assertions, stimulus strategies, and coverage models for frontend microarchitecture and its corner cases.
• Drive verification of branch prediction structures and flows, including direction prediction, indirect target prediction, return prediction, predictor update/training behavior, redirect generation, recovery, and interaction with global history or related predictor state.
• Drive verification of instruction fetch behavior, including fetch packet correctness, PC sequencing, fetch ordering, ITLB/translation interactions, exception reporting, cache-related fetch behavior, and redirect handling after misprediction or flush conditions.
• Partner with architects and designers from early feature-definition stages to review specifications, identify ambiguity, and improve frontend debugability and verification completeness.
• Drive block-level and core-level verification closure for frontend features, including coverage analysis, gap identification, bug triage, and signoff readiness.
• Apply the right verification method for the problem, including simulation, formal techniques, and emulation where appropriate for high-risk or hard-to-observe frontend behaviors.
• Mentor engineers across the organization and shape reusable verification approaches, infrastructure, and methodology for future CPU core generations.

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 12+ years of relevant experience in CPU/core or SoC functional verification, with substantial experience in high-performance CPU verification appropriate for a Principal / T6 role.
• Direct experience with out-of-order CPU core verification and strong understanding of CPU microarchitecture.
• Deep expertise in CPU frontend verification, especially branch prediction and instruction fetch verification.
• Strong knowledge of verification flow methodology, including test planning, stimulus generation, failure analysis, coverage analysis, and coverage closure.
• Strong debug skills and the ability to translate architectural intent into an effective verification strategy and execution plan.
• Strong software and scripting fundamentals for building scalable DV infrastructure, automation, and analysis workflows.

• Experience verifying advanced frontend architectures or decoupled fetch/prediction pipelines in high-performance CPU cores.
• Experience with branch prediction microarchitecture such as BTB-style structures, target prediction, return prediction, global-history-based prediction, predictor training, and misprediction recovery.
• Experience using formal verification to target bounded, control-heavy, or interface-sensitive frontend problems.
• Experience using emulation or other acceleration techniques to improve turnaround on large CPU verification workloads.
• Experience collaborating across architecture, performance, compiler, system verification, and software teams to close verification gaps from multiple perspectives.
• Demonstrated technical leadership through mentoring, methodology influence, and cross-team execution on complex CPU verification efforts.

• Frontend verification plans capture real architectural and microarchitectural risks early and completely.
• Difficult branch prediction, fetch, redirect, and recovery bugs are found early, debugged efficiently, and closed with durable solutions.
• Verification quality improves across the broader CPU DV organization through stronger methodology, reusable infrastructure, and clear technical leadership.
• Architecture, design, and DV teams rely on this engineer to solve the most complex frontend verification challenges in high-performance CPU development.