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Senior SoC Network Subsystem Architect

Job in Santa Clara, Santa Clara County, California, 95053, USA
Listing for: Intel Corporation
Full Time position
Listed on 2026-06-20
Job specializations:
  • Software Development
    Software Architect
Salary/Wage Range or Industry Benchmark: 164470 - 269100 USD Yearly USD 164470.00 269100.00 YEAR
Job Description & How to Apply Below

About the Role

The CEG NAG (Networking Architecture Group) is Intel's premier team focused on defining the future of high‑performance networking silicon. Our team architects next‑generation networking solutions that enable hyperscale data centers, cloud infrastructure, and AI workloads to achieve unprecedented performance and efficiency. We specialize in IPU/DPU platforms, advanced packet processing architectures, and programmable networking technologies that form the backbone of modern distributed computing systems.

We are seeking a Senior SoC Network Subsystem Architect to define and lead the architecture of high‑performance network subsystems for next‑generation IPU/DPU platforms. This role focuses on designing scalable, programmable networking pipelines that support hyperscale and cloud data center workloads. You will drive the end‑to‑end Network Subsystem (NSS) architecture, including packet processing pipelines, protocol engines, QoS frameworks, and observability features. This is a highly cross‑functional leadership role requiring deep technical expertise and strong collaboration across hardware, software, and systems teams.

What

You’ll Do
  • Network Subsystem Architecture Definition
    • Own end‑to‑end NSS architecture, including packet processing pipelines, protocol engines, and interface datapaths
    • Architect high‑performance packet pipelines supporting hundreds of millions of packets per second throughput and processing flows
    • Drive architectural direction for programmable vs. fixed‑function pipeline balance and future extensibility
    • Specify network subsystem pipeline scaling strategies and define multi‑generation NSS architecture roadmap
    • Lead design decisions for pipeline partitioning, feature scalability, and backward compatibility
  • QoS, Scheduling, and Flow Management
    • Architect advanced scheduling frameworks (per‑flow shaping, multi‑level scheduling, traffic class isolation)
    • Define QoS models to support multi‑tenant workloads, virtualization, and service chaining
  • Debug, Telemetry, and Observability
    • Define architecture for telemetry, performance counters, and real‑time observability of pipeline behavior
    • Architecture support for field debugging, failure triage, and large‑scale deployment monitoring
  • Cross‑Functional Leadership
    • Collaborate across SoC, compute, memory, SW/FW, validation, and customer teams to drive architecture closure
    • Interface with external customers to translate workload requirements into NSS architecture decisions
    • Lead architectural reviews and influence cross‑team technical direction
Behavioral Traits
  • Strategic thinker:
    Ability to define long‑term architecture vision and align stakeholders
  • Technical leadership:
    Influences across teams without direct authority
  • Problem solver:
    Approaches complex system challenges with structured thinking
  • Collaboration:

    Builds strong partnerships across engineering disciplines
  • Customer‑focused mindset:
    Translates real‑world workload needs into solutions
  • Adaptability:
    Navigates ambiguity and evolving technical requirements
  • Ownership mindset:
    Drives initiatives from concept through execution
Qualifications
  • Minimum Qualifications
    • Bachelor’s degree in Electrical/Computer Engineering, Computer Science or related degree with 7+ years of experience
    • 7+ years of experience in Networking ASIC / SoC / IPU / DPU architecture
    • High‑speed packet processing pipelines experience
    • Experience with system‑level architecture tradeoffs
    • Define and deliver architecture for large‑scale data center networking systems
  • Preferred Qualifications
    • Experience with programmable datapath architectures (P4, pipeline microcode, or hybrid models)
    • Experience with AI/HPC scale‑out networking and congestion control architectures
    • Transport protocols offloads, QoS, scheduling, and multi‑tenant isolation
    • Familiarity with coherent or shared‑memory offload models (e.g., CPU‑IPU integration)
    • Experience with hyperscaler deployments or customer co‑design engagements
Job Details

Job Type: Experienced Hire, Shift: Shift 1 (United States of America)

Primary

Location:

Santa Clara, California. Additional Locations:
Phoenix, Arizona;
Folsom, California;
San Jose, California;
Hillsboro, Oregon;
Austin, Texas.

Annual Salary Range: $164,470 –…

Position Requirements
10+ Years work experience
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