Senior ASIC VLSI Synthesis and Design Engineer
Job in
Santa Clarita, Los Angeles County, California, 91350, USA
Listed on 2026-06-02
Listing for:
Saxon Global
Full Time
position Listed on 2026-06-02
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer, Software Engineer
Job Description & How to Apply Below
- Bachelor's degree with 8+ years of experience OR Master's degree with 6+ years in EE, CS, IT, or related field.
- 8+ years of ASIC/VLSI design experience focusing on synthesis and timing closure for large-scale designs in deep submicron technology.
- Expertise in Verilog/System Verilog RTL coding and constraint development for synthesis.
- Proficiency with synthesis tools (Cadence, Synopsys, Mentor).
- Experience with gate-level simulation, STA, and power-aware synthesis.
- Strong post-silicon debug and validation skills, including production bring-up and failure analysis.
- Proficiency in scripting languages (Tcl, Perl, Python) for automation and flow optimization.
- Excellent problem-solving and collaboration skills in a fast-paced environment.
Position Requirements
10+ Years
work experience
To View & Apply for jobs on this site that accept applications from your location or country, tap the button below to make a Search.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
Search for further Jobs Here:
×