Senior ASIC VLSI Synthesis and Design Engineer

Job Title

Bachelor’s degree with 8+ years of experience OR Master’s degree with 6+ years in EE, CS, IT, or related field.

8+ years of ASIC/VLSI design experience focusing on synthesis and timing closure for large-scale designs in deep submicron technology.

Expertise in Verilog/System Verilog RTL coding and constraint development for synthesis.

Proficiency with synthesis tools (Cadence, Synopsys, Mentor).

Experience with gate-level simulation, STA, and power-aware synthesis.

Strong post-silicon debug and validation skills, including production bring-up and failure analysis.

Proficiency in scripting languages (Tcl, Perl, Python) for automation and flow optimization.

Excellent problem-solving and collaboration skills in a fast-paced environment.