ASIC Validation Engineer

Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI. Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference.

We do this while simultaneously reducing capital and power costs and improving reliability.

The company’s solutions and value proposition have been widely validated by leading hyperscalers.

Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co‑founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro‑LED company).

The company is in execution mode and has a world‑class engineering team with decades of experience in state‑of‑the‑art silicon, packaging, optics, software, and systems. Eridu is working with best‑in‑class supply chain partners including silicon, packaging and systems.

We are hiring multiple positions from Sr. Engineer to Principal Engineer.

We are looking for a highly experienced Post‑Silicon ASIC Validation Engineer with deep expertise in networking ASICs and chiplet‑based architectures. You will lead bring‑up, validation, and characterization of complex multi‑die systems integrating high‑speed interconnects such as UCIe, Ser Des, PCIe, and Ethernet PHYs. This position offers the opportunity to work on next‑generation networking SoCs and disaggregated chiplet platforms, collaborating across architecture, design, firmware, and system teams to ensure first‑silicon success and robust product readiness.

• Drive post‑silicon validation and bring‑up of networking ASICs and chiplet‑based SoCs.
• Own validation planning, coverage definition, and test execution across UCIe, Ser Des, and networking subsystems.
• Develop automation and test infrastructure for high‑speed link and protocol validation (Python).
• Perform silicon bring‑up, including power sequencing, link training, and PHY initialization.
• Execute link‑level and system‑level validation of UCIe interfaces, die‑to‑die interconnects, and high‑bandwidth chiplet fabrics.
• Debug complex cross‑domain issues spanning RTL, firmware, analog PHY, and package‑level interactions.
• Characterize signal integrity, latency, throughput, and thermal/power behavior across PVT corners.
• Collaborate with board design and test engineering teams on validation platforms, sockets, and characterization boards.

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• Experience in post‑silicon validation and bring‑up of complex ASICs or SoCs.
• Hands‑on experience with UCIe, PCIe and high‑speed interconnect standards.
• Proficiency in Python for scripting, automation, and data analysis.
• Strong lab experience using oscilloscopes, BERTs, logic analyzers, and JTAG‑based debuggers.
• Excellent communication skills and experience working in cross‑functional silicon development teams.

• Experience with chiplet‑based systems, UCIe protocol stack validation, and multi‑die integration challenges (power delivery, timing, thermal).
• Familiarity with emulation or FPGA prototyping platforms for pre‑silicon validation.
• Exposure to hardware/software co‑validation for networking protocols or control‑plane software.
• Strong knowledge of package‑level interactions and signal integrity analysis for high‑speed interfaces.

At Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world‑class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.

The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.

The pay range for this role is:

185, USD per year (San Francisco Bay Area)