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DV Engineer

Job in Saratoga, Santa Clara County, California, 95071, USA
Listing for: E-Space SAS
Full Time position
Listed on 2026-06-14
Job specializations:
  • Engineering
    Systems Engineer
Salary/Wage Range or Industry Benchmark: 120000 - 220000 USD Yearly USD 120000.00 220000.00 YEAR
Job Description & How to Apply Below
Position: Staff DV Engineer

Overview

Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place!

E‑Space is bridging Earth and space to enable hyper‑scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly‑advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems.

We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space‑based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life.

Position Details

This is a full‑time, exempt position based out of our Saratoga office. The target base pay for this position is $120,000 – $220,000 annually. Total compensation will be determined by job‑related knowledge, skills, and experience.

E‑Space is not currently able to provide employment sponsorship for candidates who do not hold work authorization for the location of this role.

Additional hours, including nights and weekends, may be required to meet critical deadlines and mission goals.

Requirements
  • HDL & Verification Methodology
    • Strong proficiency in Verilog and System Verilog.
    • Experience writing tests within an existing UVM verification environment.
    • Solid understanding of UVM architecture and methodology.
  • Programming & Scripting
    • Ability to write C/C++ code for verification purposes.
    • Some scripting experience in Perl or Python.
  • Verification Planning & Execution
    • Ability to contribute to and help write test plans.
    • Experience writing and maintaining verification tests.
    • Ability to debug RTL simulations independently.
  • Leadership
    • Experience leading design verification efforts at the block level.
    • Experience driving code coverage closure on assigned blocks.
What you bring to this role
  • 6+ years of design verification experience in the semiconductor industry.
Benefits
  • Opportunity to make a meaningful impact in a high‑growth industry.
  • Sustainability at our core.
  • Fair and honest workplace.
  • Encouragement of innovative thinking.
  • Competitive salaries.
  • Continuous learning and development.
  • Health and wellness care options.
  • Financial solutions for the future.
  • Optional legal services (US only).
  • Paid holidays.
  • Paid time off.
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