Architecture & Performance Modeling Engineer

Overview

About Eridu Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver faster AI. The company focuses on innovations across silicon, packaging, software, and systems to improve performance and GPU utilization while reducing capital and power costs. Eridu has raised over $200M and is led by a veteran team with experience delivering billion-dollar product lines and exits.

The company is in execution mode with a world-class engineering team and is working with leading supply chain partners. Visit eridu.ai to learn more.

We are seeking a highly skilled and visionary Performance Modeling Engineer to drive the definition, development, and application of Eridu AI’s architectural and performance modeling infrastructure. You will set the direction for modeling efforts that influence ASIC architecture and microarchitecture (uArch) designs, collaborate with system architects, chip designers, and cross-functional teams to evaluate design trade-offs, identify bottlenecks, and deliver actionable insights that shape the future of large-scale AI networking.

• Participate in the development and deployment of high-level performance models for networking devices to guide architectural decisions.
• Define modeling methodologies and frameworks that ensure consistency, accuracy, and scalability across projects.
• Partner closely with ASIC architects and uArch teams to evaluate trade-offs in throughput, latency, power, and area.
• Drive performance analysis and bottleneck identification to inform and influence architecture and design choices.
• Oversee the creation and validation of structural and traffic models to explore real-world workloads and system scenarios.
• Establish and champion best practices for performance modeling, documentation, and reporting.
• Communicate modeling results, insights, and recommendations to senior technical and leadership stakeholders.

• MSEE/PhD in Electrical Engineering, Computer Engineering, or a related field with 10+ years of relevant industry experience.
• Proven track record of technical leadership in performance modeling or architecture for ASICs, SoCs, or networking systems.
• Deep expertise in networking protocols such as Ethernet and PCIe.
• Proficiency in modeling languages and tools, including C, C++, Python, and scripting environments.
• Strong background in FPGA/ASIC design flows, including synthesis, simulation, and verification tools (e.g., Verilog, VHDL, Synopsys, Cadence).
• Demonstrated ability to drive architectural discussions and influence design trade-offs through modeling insights.
• Excellent analytical and problem-solving abilities with a data-driven approach.
• Strong communication skills with the ability to present complex technical information clearly and persuasively.

At Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.

The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.

Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.

The pay range for this role is 210, USD per year (Eridu HQ).