Advanced Packaging Engineer

About Eridu

Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI. Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference.

We do this while simultaneously reducing capital and power costs and improving reliability.

The company’s solutions and value proposition have been widely validated by leading hyperscalers.

Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company).

The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems.

Visit our website eridu.ai to learn more.

We are seeking a highly experienced Advanced Package Engineer to lead system module packaging and advanced single chip Flip Chip IC integration for next-generation high-performance networking and compute platforms.

This role owns the end-to-end productization of composite system modules assembly, driving manufacturing readiness and product implementation consisting of organic interposers, organic substrates, cooling solutions, boards, and mechanical hardware. You will architect and deliver complete module packaging assembly solutions. This role also owns leading flip‑chip single‑die Flip Chip packages and advanced 2.5D integration.

You will operate as the technical owner of system module packaging, working hands‑on with contract manufacturers, substrate vendors, OSATs, foundry partners, and internal silicon/system teams to translate ambitious architectures into high-volume, production‑ready products.

This is a highly visible technical leadership role for an engineer who thrives at the intersection of system architecture, packaging design, mechanical modeling, manufacturing, and qualification.

Own the full lifecycle of system module packaging assembly integration from architecture through volume production consisting of organic interposers, organic substrates, cooling solutions, boards, and mechanical hardware:

• Lead module manufacturing and integration with contract manufacturers and internal engineering teams.
• Own system module packaging qualification using Mechanical Test Vehicles (MTVs).
• Drive module construction architectures, BOMs, and design approvals.
• Drive mechanical modeling activities including warpage, stress, and coplanarity.
• Plan and execute module builds, assembly setup, yield learning, and yield data collection.
• Lead module qualification, failure analysis, root cause identification, and corrective action closure.
• Drive PCB SMT assembly DOE, yield tracking, and continuous improvement initiatives.
• Evaluate PCB SMT rework processes using real sample parts and production data.
• Define and validate organic substrate rework strategies.
• Propose and sign off daisy‑chain layouts for organic substrates.
• Own regular technical engagement cadence with manufacturing partners.
• Establish SMT yield goals, operational metrics, and improvement roadmaps.
• Productize module assembly with system integration partners.
• Lead module manufacturing readiness reviews and execution.
• Drive SMT soldering technology innovation through test vehicles.
• Perform manufacturing risk mitigation, and schedule alignment.
• Design and support module‑level warpage experiments and mitigation strategies.