Senior DV Engineer
Job in
Saratoga, Santa Clara County, California, 95071, USA
Listed on 2026-06-20
Listing for:
Espace
Full Time
position Listed on 2026-06-20
Job specializations:
-
Engineering
Job Description & How to Apply Below
Position
Digital Design Verification Engineer - Satellite & Wireless Telephony
ResponsibilitiesVerify custom ASICs for satellite and wireless telephony. Provide verification tests within existing environment and utilize AI assistance when possible.
Qualifications- Proficiency in Verilog and System Verilog
- Working knowledge of UVM architecture and methodology
- Experience writing verification tests within an existing environment
- Some scripting experience in Perl, Python, or bash
- VHDL knowledge is valuable
- 4+ years of design verification experience in the semiconductor industry
Full time, exempt.
Location:
Saratoga, CA. Target base pay: $120,000-$220,000 per year.
We do not provide employment sponsorship for candidates without work authorization for this location.
Benefits- An opportunity to make a difference
- Sustainability at our core
- Fair and honest workplace
- Innovative thinking encouraged
- Competitive salaries
- Continuous learning and development
- Health and wellness care options
- Financial solutions for the future
- Optional legal services (US only)
- Paid holidays
- Paid time off
Position Requirements
10+ Years
work experience
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