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Senior DV Engineer - Space ASIC Verification & Leadership
Job in
Saratoga, Santa Clara County, California, 95071, USA
Listed on 2026-06-20
Listing for:
Espace
Full Time
position Listed on 2026-06-20
Job specializations:
-
Engineering
Test Engineer, Electronics Engineer
Job Description & How to Apply Below
Espace in Saratoga is seeking a Digital Design Verification Engineer with over 10 years of experience in the semiconductor industry. Responsibilities include verifying ASICs for satellite and wireless telephony, building UVM verification environments, and debugging simulations.
The role requires expertise in Verilog, System Verilog, and proficiency in C/C++ along with strong scripting skills. The position offers competitive salaries and a chance to contribute to innovative space-based communications.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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