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Senior ASIC DV Engineer LEO Satellite – AI-Driven
Job in
Saratoga, Santa Clara County, California, 95071, USA
Listed on 2026-06-20
Listing for:
Espace
Full Time
position Listed on 2026-06-20
Job specializations:
-
Engineering
Electronics Engineer, Test Engineer, Systems Engineer
Job Description & How to Apply Below
Espace is seeking a Digital Design Verification Engineer to verify custom ASICs for low Earth orbit satellites in Saratoga, California. The ideal candidate will have a strong background in ASIC verification, particularly in satellite or wireless environments, and proficiency in Verilog and System Verilog.
This full-time, exempt role targets a base pay of $120,000 to $220,000 annually based on experience. Benefits include competitive salaries, health care options, and paid time off.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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