RTL Engineer, Networking ASIC

Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI. Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance, unlock greater GPU utilization, and speed training job completion times and tokens-per-second for more profitable inference while simultaneously reducing capital and power costs and improving reliability.

Eridu has raised over $200M and is led by a veteran team of Silicon Valley executives with multiple billion dollar product launches. The company is in execution mode and has a world-class engineering team with decades of experience in state‑of‑the‑art silicon, packaging, optics, software, and systems.

We are seeking experienced RTL designers to help define and implement our industry‑leading Networking ASICs. As part of the Design Group, you will be responsible for specifying, architecting, executing, and productizing cutting‑edge Networking chips.

• Packet buffering, queuing, and scheduling:
  Design microarchitecture and implementation of high‑speed networking ASICs, focusing on latency optimization and QoS support. Prior experience with on‑chip memory subsystems and scheduling/arbitration design.
• Implementation and Testing:
  Implement designs on ASIC platforms and ensure compliance with industry standards and performance benchmarks. Collaborate with verification teams to conduct thorough testing and validation.
• Performance Optimization:
  Analyze and optimize pipelining architectures to improve performance metrics.
• Protocol Support:
  Provide support for Ethernet, IP protocols, and high‑speed interconnects such as UCIe.
• Troubleshooting and Debugging:
  Investigate and resolve complex packet‑queuing issues alongside system architects, hardware engineers, and firmware developers.

• ME/BE with a minimum of 8–15 years of experience.
• Hands‑on knowledge of System Verilog and Verilog.
• Solid understanding of ASIC design methodologies: simulation, verification, synthesis, and timing adjustments.
• Proven expertise in designing and optimizing scheduling and QoS mechanisms.
• Experience with Ethernet and IP protocols.
• Strong analytical and problem‑solving skills with meticulous attention to detail in troubleshooting complex networking issues.
• Excellent verbal and written communication skills, and the ability to collaborate effectively in a team environment and present technical information to diverse audiences.

At Eridu, you’ll shape the future of AI infrastructure, working with a world‑class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.

The starting base salary for the selected candidate will be established based on relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles. The pay range for this role is 210,000–275,000 USD per year (San Francisco Bay Area).