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Senior ASIC Design Lead: RTL to Tapeout
Job in
Saratoga, Santa Clara County, California, 95071, USA
Listed on 2026-07-15
Listing for:
Eridu AI
Full Time
position Listed on 2026-07-15
Job specializations:
-
Engineering
Hardware Engineer, Test Engineer, Electronics Engineer
Job Description & How to Apply Below
Eridu AI, a Silicon Valley–based hardware startup, seeks a hands‑on ASIC Chip Design Lead to own RTL, micro‑architecture, and full‑chip integration from spec to signoff in a fast‑paced environment in Saratoga, CA.
You will drive RTL development in Verilog/System Verilog, collaborate with Physical Design on timing closure, and guide tape‑out efforts. Base salary range 250,000–280,000 USD per year; market practices apply.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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